# Design and Implementation of FFT Processor Using Vedic Multiplier With High Throughput

@inproceedings{Agarwal2013DesignAI, title={Design and Implementation of FFT Processor Using Vedic Multiplier With High Throughput}, author={Jyoti Agarwal and Vijay Matta and Dwejendra Arya}, year={2013} }

In present scenario every process should be rapid, efficient and simple. Fast Fourier transform (FFT) is an efficient algorithm to compute the N point DFT. It has great applications in communication, signal and image processing and instrumentation. But the Implementation of FFT requires large number of complex multiplications, so to make this process rapid and simple it's necessary for a multiplier to be fast and power efficient. To tackle this problem Urthva Tirvagbhyam in Vedic mathematics is… Expand

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#### 6 Citations

DESIGN OF FFT ARCHITECTURE USING KOGGE STONE ADDER

- Computer Science
- International Journal of Advances in Signal and Image Sciences
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An efficient Fast Fourier Transform (FFT) algorithm is used in the Orthogonal Frequency Division Multiplexing (OFDM) applications in order to compute the discrete Fourier transform. Also, a Single… Expand

VLSI IMPLEMENTATION OF VARIABLE BIT RATE OFDM TRANSCEIVER SYSTEM WITH MULTI-RADIX FFT/IFFT PROCESSOR FOR WIRELESS APPLICATIONS

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In this paper, a Variable Bit Rate 64 Subcarrier OFDM Transceiver system is implemented in FPGA and the Modified Multi-radix 64 point FFT/IFFT blocks present in the OFDM design is intended for… Expand

An Area Effective OFDM Transceiver System with Multi-Radix FFT/IFFT Algorithm for Wireless Applications

- 2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS)
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An area effective Orthogonal Frequency Division Multiplexing (OFDM) transceiver design with Multi-radix FFT/IFFT algorithm is introduced for wireless applications. The Pseudo-Random Binary Sequence… Expand

Implementation of LMS-ALE Filter using Vedic Algorithm

- Computer Science
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Vedic multipliers gives more performance in areas like resource utilization, power requirement, delay etc. when compared to conventional booth multiplier based LMS-ALE filter units. Expand

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This work synthesises high performance integer multiplier designs suitable for high speed reconfigurable VLSI systems. Various designs of integer multipliers are taken and are compared on the basis… Expand

Improved performance of FFT based cardiac analyzer using Advanced booth algorithm

- Computer Science
- 2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB)
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It is proved that the proposed FFT analyzer improved the overall performance of existing system. Expand

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